RTLDebug
This is the top level specification for RTLDebug, an open specification for in-system debugging of RTL logic in FPGA and/or ASIC.
RTLDebug defines register interfaces and architecture only, multiple implementations are possible and should interoperate as long as they conform to this specification.
Overview
An RTLDebug system consists of the following base components:
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A 32 bit memory mapped bus
The choice of bus is implementation defined; plausible choices include AMBA APB, Avalon, or Wishbone.
Registers in RTLDebug are all 32 bits in size, aligned to 32-bit boundaries (i.e. address base+0, base+4, base+8), and accessed as whole words only to provide maximum flexibility for different bus architectures.
All debug components live on this single bus. The bus may be dedicated to debug or shared with other components. -
A bridge to access this bus from a host PC
Any mechanism which allows a PC to read and write registers via JTAG, UART, or another convenient transport can be used; host-side software should be designed in a modular fashion so that transports can be easily swapped out. Self-hosted debug is possible as well, if the system is a SoC containing a processor.
The intent is to define our own open bridge standard with a freely licensed reference implementation, but to also support implementations which choose to use proprietary bridges such as an ARM JTAG-DP and MEM-AP.
The bridge provides an implementation-defined mechanism for discovering the address of the top level RTLDebug descriptor ROM table. -
A debug server on the PC
The debug server connects to the hardware bridge block (which typically only supports one concurrent connection) and exposes an API for debug software on the PC to communicate with individual debug cores. The reference implementation of the debug server exposes a SCPI instrument server on a separate TCP port for each debug core however other designs are possible. -
A top-level component descriptor ROM
The ROM contains identifiers and pointers to other debug components on the bus so that the debug server can discover what debuggable components exist. -
One or more debug cores
Individual debug cores provide debug capabilities such as signal generation, waveform capture, etc.