GPIO

[!IMPORTANT] This section describes the behavior of an existing, widely deployed block, and cannot be changed in incompatible ways.

The GPIO block uses FOURCC tag "GPIO" and provides a single bank of up to 32 general-purpose I/O pins, which may go to physical I/O pads or internal test points within the device as needed.

No symbol table is provided; this block is intended to be small and efficient rather than full-featured. If multi-bit ports or named signals are needed, use the VIO block instead.

Registers

Each GPIO is controlled by one bit each of the OUT, IN, and TRIS registers.

• OUT: value to drive out the port when configured in output mode, ignored when in input mode
• IN: value seen by the port when configured in input mode. The value when the pin is configured as an output is IMPLEMENTATION DEFINED.
• TRIS: 1 for input, 0 for output

Notes

If these pins drive physical GPIO pads rather than internal nodes, I/O buffer configuration (pullup/pulldown, drive strength, etc) is provided by an IMPLEMENTATION DEFINED mechanism.

If the GPIO block is connected to internal nodes that do not support tristates, an implementation MUST ignore the value of the TRIS register. In this case, an implementation MAY choose to do any of the following:

• Tie IN and OUT together for output-only ports
• Tie IN to a constant value for output-only ports
• Use IN and OUT as independent 32-bit unidirectional ports